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[1-4]
| Order by:
[Title],
[Author],
[Editor],
[Year] |
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C. R. Hardnett, R. M. Rabbah, K. V. Palem, W. F. Wong
Cache Sensitive Instruction Scheduling
Center for Research in Embedded Systems and Technologies, Georgia Institute of Technology, 2001 |
Theory & Techniques:
Code Optimization, Data Flow Analysis
|
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Allen Leung, Krishna V. Palem, Cristian Ungureanu
Run-Time versus Compile-Time Instruction Scheduling in Superscalar (RISC) Processors: Performance and Trade-Off
Article in
Journal of Parallel and Distributed Computing, 1997 |
Theory & Techniques:
Code Optimization, Data Flow Analysis
|
|
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R. Motwani, K. V. Palem, V. Sarkar, S. Reyen
Combining Register Allocation and Instruction Scheduling: (Technical Summary)
Courant Institute, New York University, 1995 |
Theory & Techniques:
Code Optimization, Data Flow Analysis
|
|
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K. V. Palem, B. Simons
Scheduling Time-critical Instructions on RISC Machines
Article in
ACM Transactions on Programming Languages and Systems, 1993 |
Theory & Techniques:
Code Optimization, Data Flow Analysis
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